WP32 Board Specification

Rev B November, 2003

Overview

The WP32 board houses 32 transmit / receive channels and is designed to form part of a stack of multiple WP32s to form an Ultrasonic Scanner System. The functions of beamforming, correlation, scan conversion and communication to a PC over a USB2.0 port are incorporated. Interconnect boards are available that connect 2, 4, 10 and 16 WP32s into a system and to various transducers. A cases are available to house working solutions of one to four of the WP32 boards, interconnectboards, power supply and connections.

Each channel on the WP32 comprises a pulser, a pre-amplifier, 80dB of time gain compensation at 90 MHz bandwidth and a 12-bit 40 MHz analog converter. The ADCs are fed directly into a large Field Programmable Gate Array where dynamic delay line summation is performed in parallel to produce multiple acoustic lines. The acoustic lines may be stored into frames then scan converted and transferred to a PC for display at up to 20 Mbytes per second. The WP32 also contains an additional large FPGA to perform more complex cross-correlation of the acquired acoustic lines in real time.

The board requires 12 volts, 5 volts and up to 16 pulser voltages from a separate WinProbe supply. All other functions are either on board or programmed through a PC interface. Default WinProbe algorithms for beamforming, correlation and scanconversion algorithms are loaded in memory on the board but researchers may reprogram the algorithms through the PC interface.

As of this date the hardware is operational but not field released. Most functions described herein are operational but must be considered under development. WinProbe is offering the hardware as a research tool to interested parties who are willing to evaluate functional development of algorithms in both the PC software and the VHDL code of the FPGAs. Relationships can be accommodated where ownership of the non-WinProbe intellectual property is preserved. Reprogramming of the FPGAs is currently accomplished in industry standard VHDL code. Future improvements will allow researchers to reprogram the FPGAs from MatLab.

The Pulser

The WP32 board is equipped with 32 pulsers each capable of +/-100 volt transitions with 16 voltage levels of user programmable transmit codes held in an onboard memory that is loaded from the PC. The clock rate for the memories is 10ns, which corresponds to the time granularity of all codes given to the pulser. Each channel pulser can be programmed to transmit one of the 16 voltages for apodization during transmission. Multiple instantly selectable transmission protocols of up to 8000 transition clocks per transmission for each channel are held in the pulser memory.

The Receiver

The WP32 is equipped with 32 receiver channels with individual Time Gain Compensation in 256 linear steps over the 80dB range (0.32dB per step +/- 1dB accuracy). Switches are provided for transmit protection but each channel is also intended to input pre-amplified input. A clock of 1/16 the ADC clock updates the Digital to Analog Conversion for each TGC selection and this wave file is loaded from the PC and stored in memory. Multiple instantly selectable wave files may be stored.

The Digitization

The WP32 houses 32 12bit 40 MHz Flash Analog to Digital Converters. These may be clocked at any frequency up to 40 MHz. They may be phased relative to each other with a 12.5 ns granularity.

The Beamformer Receive Focus (programmed into FPGA1)

The WP32 may share data with up to 4 other boards to form a beam from up to 128 channels with a dynamic focus delay of up to 12 m seconds. Apodization and delays are programmed into an on board memory from the PC. Sub ADC clock interpolation may be implemented as required.

The scanconversion function is firmware and is downloaded from the PC. The standard algorithm is a bi-linear interpolation from the scan domain into the video domain. A 512 by 480 video output frame is standard. Optimized video frames can be implemented. Multiple simultaneous video flows can be implemented to display multiple scan domains. A maximum data rate of 60 frames per second of 512 by 480 pixels is possible.

The USB Port

The USB2 port is a standard Cypress implementation. For multiple WP32 stacks only one USB2 cable connection is required and this will function a to configure all the boards and also be the channel for all the video data.

(It is possible to have multiple video data channels to multiple PCs but this is not in the near term development program. The USB2 port is functional up to 20 Mbytes per second dependent on the PC and its interface.)

The Correlation Engine (programmed into FPGA2)

The WP32 is equipped with two, 2 to 8 million gate FPGAs and support memory to provide the function of correlation. Acoustic lines in the form of RF data are selected by the engine and cross-correlated. Many algorithms can be supported but the primary algorithm in WinProbe's library is a user selectable kernel length and kernel offsets that are used to form the Sum of the Products (SOP) between two lines. The SOP is transferred to a Peak Detector and the shift and correlation magnitude are supplied for every ADC clock at the ADC clock rate delayed by a pipeline of clocks not greater than kernel length plus 25.

[Typical kernel lengths are 32-50 (1-2mm) samples and an offset of plus and minus 1 sample clock (38 microns) run in three simultaneous SOP engines to allow the Peak Detector to interpolate a shift peak to 128th of a sample clock interval (0.3micron).]

Ultrafast Imaging

The April 2004 Revision of the WP32 board will offer 168-pin DIMM sockets between the ADC and the Beamformer Receive Function housed in FPGA1. If populated with 512 Mbyte memory sticks these memories will allow 256 Mega samples to be stored for each channel. This will accommodate up to 6000 RF acoustic frames per second. Optimal memory allocation can be programmed from the PC to suit the study (line length or study length). The memories can be individually clocked and the data read out as FIFO or LIFO.

SPECIFICATIONS OF WP32 BOARD

The specifications are the product of the hardware, the firmware and the software and the following is what is and will be supported by WinProbe algorithms.

Dimensions 13 x 10.5 x 0.75 inches (33 x 26.67x1.9 cm)
Power 12 volts @ up to 2 amps and 5 volts @ up to 8 amps.
Transmit Max Center Frequency MHz 30
Digital band width MHz 30
Maximum Peak Voltage Volts +/-100
Waveform Increments ns 10
Amplitude Variability Volts 6
Max Number of transmit edges / protocol 8000
Receive ADC clock (variable from DC to 40MHz)
ADC depth bits 12
TGC range dB 80
Noise level 3.5 nV sq rt Hz 3.5
Max Delay ADC clocks 512
Min (non interpolated delay) ns 25
Maximum scan length words 8Kx18
Beamformer Maximum no of channels 256
Number of simultaneous receive beams @40MHz 3
Linear interpolation of delay at 25ns ns 8.3
Apodization defined by PC table
Focus defined by PC table
Scan conversion sample data matrix size user definable
Video matrix size user definable (default is 512 x 480 pixels)
Scan conversion method user definable (default is nearest neighbors bi-linear).